This invention relates generally to the routing of data between bus devices in a computer system and more particularly relates to data routing between bus devices in a switch based topology where existing status/response protocol signals on the bus are used to provide routing feedback information to the switch.
Today, computer systems utilizing switch based topologies are becoming increasingly popular. In a computer system utilizing a switch based topology, each bus device (e.g., a processor, an I/O hub, or a memory controller) is directly connected to a central switch by an electrically isolated point-to-point connection. When a first bus device (e.g., a processor) wants to send data to a second bus device (e.g., an I/O hub), the switch routes the data from the source device to the correct destination device.
In order to perform the data routing between the source device and the destination device, switches typically incorporate address range registers corresponding to each bus device connected to the switch. In a typical scenario, the switch compares the addresses of incoming commands to the address range values contained within the address range registers in order to route the data corresponding to the issued command to the correct destination bus device.
Unfortunately, the use of address range registers within the switch has some significant disadvantages. In a very large system, a correspondingly large number of address range registers are required in the switch to support the large number of bus devices connected to the switch. Also, the address range associated with a single bus device may include multiple discrete address sub-ranges. As a result, a large amount of logic is required within the switch in order to perform the address compare operations. The large number of address compare operations required in such a configuration can potentially introduce timing problems at the switch. Another disadvantage of address range registers is that they must be configured by software. If a large number of address range registers are present within the switch, the software configuration of the address range registers becomes a complex and time consuming task.
Thus, there is a need for an efficient apparatus and method for routing data signals in a computer system employing a switch-based topology. The method and apparatus should be easily implementable in a minimal amount of logic. The method and apparatus should also be able to handle any configuration of bus devices without introducing any software overhead.
These and other objects, features and advantages of the present invention will be further described and more readily apparent from the summary, detailed description and preferred embodiments, the drawing and the claims which follow.
The present invention provides an apparatus and method for routing data between multiple bus devices organized in a switch based topology. In the switch based topology of the preferred embodiment, the xe2x80x9csystem busxe2x80x9d is defined by a plurality of point-to-point connections between each of the plurality of bus devices and a centralized switch. Thus, data going from a first bus device to a second device is always routed via the switch.
Upon receiving a command, each bus device within the switch based topology responds by issuing an address status response signal to a response combining logic module residing between the bus device and the switch. The response combining logic module identifies which bus device (if any) responded to the command with a positive acknowledge. The response combining logic module then sends a bus device identifier to the switch via a destination route bus identifying which bus device responded with the positive acknowledge. The switch uses the device identifier returned via the response combining logic to route any subsequent data transfers associated with the issued command.
The preferred embodiment of the present invention offers several advantages over traditional data routing schemes. In contrast to traditional routing schemes which employ address range registers embedded in the switch to direct a data transfer, the preferred embodiment utilizes address status information returned as feedback to an issued command to determine the destination device for the data transfer.
As a result, no additional logic (i.e., address range registers) needs to be incorporated within the switch, simplifying the design of the switch and increasing the operational efficiency of the switch. Additionally, since address range registers are not required by the present invention, no software overhead is required to configure the address range registers. Finally, in contrast to traditional routing schemes where most or all of the nodes within the topology are aware of the entire topology and can make routing decisions, the preferred embodiment incorporates a central control structure where only the response combining logic module is aware of the topology and it alone provides routing decisions.